hv219 doc.# dsfp-hv219 c070713 features ? hvcmos ? technology for high performance ? very low quiescent power dissipation (-10a) ? output on-resistance typically 11 ? low parasitic capacitance ? dc to 50mhz small signal frequency response ? -60db typical off-isolation at 5.0mhz ? cmos logic circuitry for low power ? excellent noise immunity ? serial shift register logic control with latches ? flexible operating supply voltages ? surface mount packages applications ? medical ul trasound imaging ? non-destructive evaluation block diagram 200v low charge injection 8-channel high voltage analog switch general description the supertex hv219 is a low switch resistance, low charge injection, 8-channel, 200v, analog switch integrated circuit (ic) intended primarily for medical ultrasound imaging. the device can also be used for nde (non-destructive evaluation) applications. the hv219 is a lower switch resistance, 11 versus 22, version of the supertex hv20220 device. the lower switch resistance will help reduce insertion loss. it has the same pin confguration as that of the supertex hv20220pj and the hv20220fg. the device is manufactured using supertexs hvcmos ? (high voltage cmos) technology with high voltage bilateral dmos structures for the outputs and low voltage cmos logic for the input control. the outputs are confgured as eight independent single pole single throw 11 analog switches. the input logic is an 8-bit serial to parallel shift register followed by an 8-bit parallel latch. the switch states are determined by the data in the latch. logic high will correspond to a closed switch and logic low as an opened switch. the hv219 is designed to operate on various combinations of high voltage supplies. for example the v pp and v nn supplies can be: +40v/-160v, +100v/-100v, or +160v/-40v. this allows the user to maximize the signal voltage for uni-polar negative, bi-polar, or uni- polar positive. sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 latches level shifters output switches vdd le cl din clk dout 8-bit shift register d le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl vnn vpp gnd supertex inc. supertex inc. www .supertex.com
2 hv219 doc.# dsfp-hv219 c070713 absolute maximum ratings parameter value v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 220v v pp positive high voltage supply -0.5v to v nn +200v v nn negative high voltage supply +0.5v to -200v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65 o c to +150 o c power dissipation: 28-lead plcc 48-lead lqfp 1.2w 1.0w operating conditions sym parameter value v dd logic power supply voltage 4.5v to 13.2v v pp positive high voltage supply 40v to v nn +200v v nn negative high voltage supply -40v to -160v v ih high level input logic voltage v dd -1.5v to v dd v il low-level input logic voltage 0v to 1.5v v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v t a operating free air temperature 0 o c to 70 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin confguration product marking yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv219pj llllllllll ccccccccccc aaa yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww hv219fg lllllllll cccccccc aaa 28-lead plcc 48-lead lqfp 28-lead plcc (top view) 48-lead lqfp (top view) 1 48 1 28 4 26 package may or may not include the following marks: si or package may or may not include the following marks: si or ordering information part number package option packing hv219fg-g 48-lead lqfp 250/tray hv219fg-g m931 1000/reel hv219pj-g 28-lead plcc 38/tube hv219pj-g m904 500/reel typical thermal resistance package ja 48-lead lqfp 52 o c/w 28-lead plcc 48 o c/w power up/down sequence 1. power up/down sequence is arbitrary except gnd must be powered up frst and powered down last. this applies for applications powering gnd of the ic with different voltages. 2. v sig must always be at or in between v pp and v nn or foating during power up/down transition. 3. rise and fall times of the power supplies v dd , v pp , and v nn should not be less than 1.0ms. -g denotes a lead (pb)-free / rohs compliant package supertex inc. www .supertex.com
3 hv219 doc.# dsfp-hv219 c070713 dc electrical characteristics (over recommended operating conditions unless otherwise noted) sym parameter 0 o c +25 o c +70 o c units conditions min max min typ max min max r ons small signal switch on-resistance - 15 - 13 19 - 24 i sig = 5.0ma v pp = +40v v nn = -160v - 13 - 11 14 - 16 i sig = 200ma - 13 - 11 14 - 15 i sig = 5.0ma v pp = +100v v nn = -100v - 9.0 - 9.0 12 - 14 i sig = 200ma - 12 - 10 13 - 15 i sig = 5.0ma v pp = +160v v nn = -40v - 11 - 8 13 - 14 i sig = 200ma r ons small signal switch on-resistance matching - 20 - 5.0 20 - 20 % i sig = 5.0ma, v pp = +100v, v nn = -100v r onl large signal switch on-resistance - - - 8.0 - - - v sig = v pp -10v, i sig = 1.0a i sol switch off leakage per switch - 5.0 - 1.0 10 - 15 a v sig = v pp -10v & v nn +10v v os dc offset switch off - 300 - 100 300 - 300 mv r load = 100k dc offset switch on - 500 - 100 500 - 500 mv r load = 100k i ppq quiescent v pp supply current - - - 10 50 - - a all switches off i nnq quiescent v nn supply current - - - -10 -50 - - a all switches off i ppq quiescent v pp supply current - - - 10 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - -10 -50 - - a all switches on, i sw = 5.0ma i sw switch output peak current - 3.0 - 3.0 2.0 - 2.0 a v sig duty cycle < 0.1% f sw output switch frequency - - - - 50 - - khz duty cycle = 50% i pp average v pp supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i nn average v nn supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i dd average v dd supply current - 4.0 - - 4.0 - 4.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq quiescent v dd supply current - 10 - - 10 - 10 a all logic inputs are static i sor data out source current 0.45 - 0.45 0.70 - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 0.70 - 0.40 - ma v out = 0.7v c in large input capacitance - 10 - - 10 - 10 pf --- supertex inc. www .supertex.com
4 hv219 doc.# dsfp-hv219 c070713 ac electrical characteristics (over recommended operating conditions, v dd = 5.0v, unless otherwise noted) sym parameter 0 o c +25 o c +70 o c units conditions min max min typ max min max t sd set-up time before le rises 150 - 150 - - 150 - ns --- t wle time width of le 150 - 150 - - 150 - ns --- t do clock delay time to data out - 150 - - 150 - 150 ns --- t wcl time width of cl 150 - 150 - - 150 - ns --- t su set-up time data to clock 15 - 15 8.0 - 20 - ns --- t h hold time data from clock 35 - 35 - - 35 - ns --- f clk clock frequency - 5.0 - - 5.0 - 5.0 mhz 50% duty cycle, f data = f clk /2 tr, tf clock rise and fall times - 50 - - 50 - 50 ns --- t on turn-on time - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k t off turn-off time - 5.0 - - 5.0 - 5.0 s dv/dt maximum v sig slew rate - 20 - - 20 - 20 v/ns v pp = +40v, v nn = -160v - 20 - - 20 - 20 v pp = +100v, v nn = -100v - 20 - - 20 - 20 v pp = +160v, v nn = -40v k o off isolation -30 - -30 -33 - - - db f = 5.0mhz, 1.0k//15pf load -58 - -58 - - - - f = 5.0mhz, 50 load k cr switch crosstalk - - -60 - - - - db f = 5.0mhz, 50 load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width, 2% duty cycle c sg(off) off capacitance sw to gnd 14 25 14 20 25 14 25 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd 40 60 40 50 60 40 60 pf 0v, f = 1.0mhz +v spk output voltage spike - - - - 150 - - mv v pp = +40v, v nn = -160v, r load = 50 -v spk - - - - 200 - - +v spk - - - - 150 - - v pp = +100v, v nn = -100v, r load = 50 -v spk - - - - 200 - - +v spk - - - - 150 - - v pp = +160v, v nn = -40v, r load = 50 -v spk - - - - 200 - - qc charge injection - - - 1450 - - - pc v pp = +40v, v nn = -160v, v sig = 0v - - - 1050 - - - v pp = +100v, v nn = -100v, v sig = 0v - - - 550 - - - v pp = +160v, v nn = -40v, v sig = 0v supertex inc. www .supertex.com
5 hv219 doc.# dsfp-hv219 c070713 data in le clock data out off on v out (typ) 50% 50% 50% 50% t wle t sd t su t h 50% 50% t off 50% t do t on t wcl clr d n+1 d n d n-1 50% 50% 90% 10% logic timing waveforms truth table data in 8-bit shift register le cl output switch state d0 d1 d2 d3 d4 d5 d6 d7 sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on x x x x x x x x h l hold previous state x x x x x x x x x h off off off off off off off off notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l to h transition clock. 3. the switches go to a state retaining their present condition at the rising edge of the le. 4. when le is low, the shift register data fows through the latch. 5. shift register clocking has no effect on the switch states if le is high. 6. the clear input overrides all other inputs. supertex inc. www .supertex.com
6 hv219 doc.# dsfp-hv219 c070713 test circuits charge injection v sig v out 1000pf q = 1000pf x v out v out switch off leakage i sol v pp 5v v nn v pp - 10v dc offset on/off v out t on /t off t est circuit v pp -10v v out isolation diode current i id v nn v sig nc 50 50 output v oltage spike v out 1.0k +v spk -v spk v in = 10v p-p @5.0mhz v out r load 50 r load 100k v nn + 10v v pp 5v v nn vpp vnn vdd gnd v pp 5v v nn v pp 5v v nn v pp 5v v nn v pp 5v v nn r load 10k v in = 10v p-p @5.0mhz k o = 20 log v out v in off isolation k cr = 20log v out v in crosstalk v pp 5v v nn vpp vnn vdd gnd vpp vnn vdd gnd vpp vnn vdd gnd vpp vnn vdd gnd vpp vnn vdd gnd vpp vnn vdd gnd r load v pp 5v v nn vpp vnn vdd gnd supertex inc. www .supertex.com
7 hv219 doc.# dsfp-hv219 c070713 pin description 48-lead lqfp pin name 1 sw5 2 nc 3 sw4 4 nc 5 sw4 6 nc 7 nc 8 sw3 9 nc 10 sw3 11 nc 12 sw2 pin name 13 nc 14 sw2 15 nc 16 sw1 17 nc 18 sw1 19 nc 20 sw0 21 nc 22 sw0 23 nc 24 vpp pin name 25 vnn 26 nc 27 nc 28 gnd 29 vdd 30 nc 31 nc 32 nc 33 din 34 clk 35 le 36 clr pin name 37 dout 38 nc 39 sw7 40 nc 41 sw7 42 nc 43 sw6 44 nc 45 sw6 46 nc 47 sw5 48 nc pin description 28-lead plcc pin name 1 sw3 2 sw3 3 sw2 4 sw2 5 sw1 6 sw1 7 sw0 pin name 8 sw0 9 nc 10 vpp 11 nc 12 vnn 13 gnd 14 vdd pin name 15 nc 16 din 17 clk 18 le 19 cl 20 dout 21 sw7 pin name 22 sw7 23 sw6 24 sw6 25 sw5 26 sw5 27 sw4 28 sw4 supertex inc. www .supertex.com
8 hv219 doc.# dsfp-hv219 c070713 48-lead lqfp package outline (fg) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-48lqfpfg version, d041309. 1 seating plane gauge plane l l1 l2 vi ew b view b seating plane top view side view note 1 (index area d1/4 x e1/4) 48 a2 a a1 b d d1 e e1 e note: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. supertex inc. www .supertex.com
9 hv219 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv219 c070713 28-lead plcc package outline (pj) .453x.453in. body, .180in. height (max), .050in. pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .485 .450 .485 .450 .050 bsc .025 nom .172 .105 - - - .490 .453 .490 .453 .035 max .180 .120 .083 .021 .032 .495 .456 .495 .456 .045 jedec registration ms-018, variation ab, issue a, june, 1993. drawings not to scale . supertex doc. #: dspd-28plccpj, version b031111. .150max .048/.042 x 45 o .075max d d1 e1 e t op vi ew v iew b a a2 a1 seating plane note 1 (index area) .056/.042 x 45 o base plane .020min b vi ew b b1 horizontal side v iew v ertical side vi ew note 2 .020max (3 places) r e 4 26 28 1 notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
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